Introduction – System Verilog Testbench

What is system verilog Testbench?

        System verilog Testbench is a collection of classes that generates input to the design and simulates the functionality given in the spec.

System verilog performs following activities:

      1. Validates design functionality.

      2. Generates stimuli.

      3. Drives stimulus required location.

      4. Compares expected and actual output.

      5. Identifies functionality errors.

      6. Helps in debugging the errors in design.

                                                                   fig: sv testbench architecture

The Testbench contains different classes of components.They are

Components	Description
Interface	Interface is a container of signals that is used between dut and testbench.
Transaction	Transaction contains required signals that need to be driven from generator to driver and driver to interface and similarly collects the signals through monitor from interface.
Generator	Generates required signals that need to send to dut
driver	Driver drives the signals received from generator to dut with respective to clock if required.
Monitor	Monitor receives the data from interface which driver sends and dut responds.
scoreboard	Scoreboard compares the actual data and expected data
Environment	Environment contains generator,driver monitor and scoreboard which performs the respective operations.
Testbench Top	Top module contains testbench environment and tests are created and initiated in this top.