System Verilog Arrays
Arrays In System Verilog
Arrays :
1. size( )
2. delete( )
Queues
Bounded Queues
Queues methods
1.size( )
2. delete( ) & delete(index)
3. insert( )
4. push( ) methods
5. pop( ) methods
Associative arrays
Associative array methods
1.size( )
2.delete ( ) & delete(index)
3.num ( )
4.exists( )
5.first( ) ,next( ), prev ( ), last( )
Common Methods for Dynamic Arrays & Queues :
Introduction
what is an array in System Verilog?
Array is a collection of data of same data type i.e all the elements present in an array will be of same data type.
The data type may be either “int” or “bit” or “byte” or “logic” or it can be “wire” type also.
–>Arrays will allow you to store multiple elements under one variable and the data type of the variable will be applicable to
all the elements of an array.
–> Arrays will provides efficient management of collection of data.
Types of Arrays in System Verilog
what are the types of arrays in system verilog ?
System Verilog uses the word “packed_array” to refer the dimensions mentioned before the variable name and it uses the word
“unpacked_array” to refer the dimensions mentioned after variable name. Packed_array and unpacked_array are two types of
arrays in system verilog.
types of arrays : 1.packed arrays
2.unpacked arrays
1.Packed arrays : The arrays whose dimensions(size) are mentioned before the varibale name are called packed arrays.
Syntax : data_type [size]variable_name;
Example : bit [3:0]addr;
bit [4:0][3:0]data;
2.Unpacked arrays : The arrays whose dimensions(size) are mentioned after the variable name are called as unpacked arrays.
syntax : data_type variable_name[size];
Example : int xtn[3:0]
–> unpacked arrays are again categorised as follows :
1. one dimensional : one dimensional unpacked arrays will have only one dimension after the variable name.
syntax : data_type varibale_name[dimension];
Example : int packet[2:0];
2.multi dimensional : Multi dimensional arrays will have more than one dimension after the variable name.
Syntax : data_type variable_name[dimension-1][dimensions-2];
Example : int xtn[2:0][3:0];
Array Assignments in System Verilog
–> Assigning of fixed-size unpacked arrays requires both source and target should have the same number of unpacked dimensions and length
of each dimension should be same.
–> Assignment is done by assigning each element of source array to corresponding element of destination array , which requires equal number
of dimensions and lengths of dimensions.
–> Assigning the unequal number of dimensions to another will result in type_check error.
Example : int xtn[100:1];
int pkt[0:99];
xtn = pkt // compatible i.e both having same size capable of holding same number of elements
–> Assigning array of wires : An array of wires can be assigned to an array of variables having the same number of unpacked dimensions
and the same length for each of those dimensions, and vice-versa.
Example : int pkt[10:1];
wire addr[0:9];
assign addr <= pkt ;
–> Assigning fixed size unpacked array to Dynamic array : A dynamic array can be assigned to a one-dimensional fixed-size array of
a compatible type, if the size of the dynamic array is the same as the length of the fixed-size array dimension.
Example : int axi_addr[100:1];
int apb_addr[ ];
int ahb_addr [ ];
apb_addr =new [ 100 ];
ahb_addr =new[ 80];
axi_addr = apb_addr ; // both have same dimension and same length of dimension
axi_addr = ahb_addr ;// error will throw as incompatible types