What is system verilog?
System Verilog is a Hardware Verification language that verifies digital and analog devices. System Verilog is built over the Verilog language (verilog-2001). System verilog improves the productivity,readability,reusability of verilog based code.System verilog is case sensitive language. System verilog is widely used in design and verification.
Note:- Design engineers develop assertions to embedd the requirements.
Verification engineers develop testcases to bound_in assertions.
Why is system verilog created?
In 1990’s, VHDL(verilog hardware description language) was widely used for describing the design architecture of hardware for synthesis and simulation. As the architecture grew VHDL was not sufficient enough to cope with the design then different languages like “openvera”,”e” were created which increased the cost of verification with different tools. This productivity crisis led to development of system verilog by Accellera with EDA tools support.
What is the difference between verilog and system verilog?
| Verilog | System Verilog |
| Verilog is a hardware description language | System Verilog is a hardware verification language. |
| Verilog is static | System verilog is static and dynamic |
| It doesnot support library management. | It supports library management. |
| It does not support OOPs concepts | It supports OOPs concept. |
| It doesnot have functional coverage. | It have functional coverage. |
| It doesnot support assertions based verification | It supports assertion based verification |
| It does not support constraint driven verification | It supports constraint driven verification |
| It is mainly used in ASIC and SOC designing | It is used in design and verification. |